SI5325C-C-GM Datasheet, PDF (13/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

Si53xx-RM
tables.
A wide range of settings are available, but they are a subset of the frequency plans supported by the Si5323 and
Si5366 jitter-attenuating clock multipliers. The Si5325 and Si5367 are microprocessor-controlled clock multipliers
that can be controlled via an I²C or SPI interface.
These devices accept clock inputs ranging from 10 MHz to 710 MHz and generate multiple independent,
synchronous clock outputs ranging from 10 MHz to 945 MHz and select frequencies to 1.4 GHz. The Si5325 and
Si5367 support a subset of the frequency translations available in the Si5319, Si5324, Si5326, Si5327, Si5368, and
Si5369 jitter-attenuating clock multipliers. The Si5325 and Si5367 can accept input clocks at different frequencies
and generate output clocks at different frequencies. The Si5322, Si5325, Si5365, and Si5367 support a digitally
programmable loop bandwidth that ranges from 150 kHz to 1.3 MHz. No external components are required for
these devices. LOS and FOS monitoring is available for these devices, as described above.
The Si5374, Si5375, and Si5376 are quad DSPLL versions of the Si5324, Si5319, and Si5326, respectively. Each
of the four DSPLLs can operate at completely independent frequencies. The only resources that they share are a
common I²C bus and a common XA/XB jitter reference oscillator. These quad devices cannot use a crystal as their
reference source. Since they require a require a free standing reference oscillator, the XA/XB reference pins were
renamed to OSC_P and OSC_N. The Si5375 consists of four one-input and one-output DSPLLs. The Si5374
consists of four two-input and two-output DSPLLs with very low loop bandwidth. The Si5376 is similar to the Si5374
with the exception that it has higher loop BW values.
The Any-Frequency Precision Clocks have differential clock output(s) with programmable signal formats to support
LVPECL, LVDS, CML, and CMOS loads. If the CMOS signal format is selected, each differential output buffer
generates two in-phase CMOS clocks at the same frequency. For system-level debugging, a PLL bypass mode
drives the clock output directly from the selected input clock, bypassing the internal PLL.
Silicon Laboratories offers a PC-based software utility, DSPLLsim, that can be used to determine valid frequency
plans and loop bandwidth settings for the Any-Frequency Precision Clock product family. For the microprocessor-
controlled devices, DSPLLsim provides the optimum PLL divider settings for a given input frequency/clock
multiplication ratio combination that minimizes phase noise and power consumption. Two DSPLLsim configuration
software applications are available for the 1-PLL and 4-PLL devices, respectively. DSPLLsim can also be used to
simplify device selection and configuration. This utility can be downloaded from http://www.silabs.com/timing.
Other useful documentation, including device data sheets and programming files for the microprocessor-controlled
devices are available from this website.
Rev. 1.2
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