SI5325C-C-GM Datasheet, PDF (25/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

Si53xx-RM
3.10. Si5365
The Si5365 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter
attenuation. The Si5365 accepts four clock inputs ranging from 19.44 MHz to 707 MHz and generates five
frequency-multiplied clock outputs ranging from 19.44 MHz to 1050 MHz. The input clock frequency and clock
multiplication ratio are selectable from a table of popular SONET, Ethernet, Fibre Channel, and broadcast video
rates. The DSPLL loop bandwidth is digitally selectable. Operating from a single 1.8, 2.5 V, or 3.3 V supply, the
Si5365 is ideal for providing clock multiplication in high performance timing applications. See "5. Pin Control Parts
(Si5316, Si5322, Si5323, Si5365, Si5366)" on page 37 for a complete description.
CKIN_1+
2
CKIN_1–
÷ N3_1
CKIN_2+
2
CKIN_2–
÷ N3_2
CKIN_3+
2
CKIN_3–
÷ N3_3
CKIN_4+
2
CKIN_4–
÷ N3_4
C1B
C2B
C3B
ALRMOUT
C1A
C2A
CS0_C3A
CS1_C4A
f3
DSPLL^®
÷ N2
Control
fOSC _{÷ N1_HS}
1
÷ NC1
0
1
÷ NC2
0
1
÷ NC3
0
÷ NC4
1
0
÷ NC5
1
0
BYPASS/
DSBL2
2 CKOUT_1+
CKOUT_1–
2 CKOUT_2+
CKOUT_2–
DBL2_BY
2 CKOUT_3+
CKOUT_3–
DBL34
DIV34[1:0]
2 CKOUT_4+
CKOUT_4–
2 CKOUT_5+
CKOUT_5–
DBL5
VDD
GND
Figure 10. Si5365 Low Jitter Clock Multiplier Block Diagram
Note: Not recommended for new designs. For alternatives, see the Si533x family of products.
Rev. 1.2
25