SI5325C-C-GM Datasheet, PDF (26/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

Si53xx-RM
3.11. Si5366
The Si5366 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including
SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5366 accepts four clock inputs ranging from 8 kHz to
707 MHz and generates five frequency-multiplied clock outputs ranging from 8 kHz to 1050 MHz. The input clock
frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, Fibre Channel,
and broadcast video (HD SDI, 3G SDI) rates. The DSPLL loop bandwidth is digitally selectable from 60 Hz to
8 kHz, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V
supply, the Si5366 is ideal for providing clock multiplication and jitter attenuation in high performance timing
applications. See "5. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)" on page 37 for a complete
description.
RATE[1:0] ^{Xtal or Refclock}
XB
XA
CKIN_1+
2
CKIN_1–
CKIN_2+
2
CKIN_2–
CKIN_3+
2
CKIN_3–
CKIN_4+
2
CKIN_4–
÷ N3_1
÷ N3_2
÷ N3_3
÷ N3_4
CK_CONF
C1B
C2B
C3B
ALRMOUT
C1A
C2A
CS0_C3A
CS1_C4A
LOL
f3
Control
fx
DSPLL^®
fOSC
÷ N1_HS
÷ N2
CKOUT_2
CKIN_3
CKIN_4
FSYNC
FSYNC
LOGIC/
ALIGN
3
1
÷ NC1
0
1
÷ NC2
0
1
÷ NC3
0
÷ NC4
1
0
÷ NC5
1
0
BYPASS/DSBL2
2 CKOUT_1+
CKOUT_1–
2 CKOUT_2+
CKOUT_2–
DBL2_BY
2 CKOUT_3+
CKOUT_3–
DBL34
DIV34[1:0]
2 CKOUT_4+
CKOUT_4–
2 CKOUT_5+
CKOUT_5–
DBL5
VDD
GND
Figure 11. Si5366 Jitter Attenuating Clock Multiplier Block Diagram
26
Rev. 1.2