SI5325C-C-GM Datasheet, PDF (31/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

Si53xx-RM
3.17. Si5375
The Si5375 is a highly integrated, 4-PLL jitter-attenuating precision clock multiplier for applications requiring sub 1
ps jitter performance. Each of the DSPLL® clock multiplier engines accepts an input clock ranging from 2 kHz to
710 MHz and generates an output clock ranging from 2 kHz to 808 MHz. Each DSPLL provides virtually any
frequency translation combination across this operating range. For asynchronous, free-running clock generation
applications, the Si5375’s reference oscillator can be used as a clock source for any of the four DSPLLs. The
Si5375 input clock frequency and clock multiplication ratio are programmable through an I2C interface. The Si5375
is based on Silicon Laboratories' third-generation DSPLL® technology, which provides any-frequency synthesis
and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter
components. Each DSPLL loop bandwidth is digitally programmable from 60 Hz to 8 kHz, providing jitter
performance optimization at the application level. The device operates from a single 1.8 or 2.5 V supply with on-
chip voltage regulators with excellent PSRR. The Si5375 is ideal for providing clock multiplication and jitter
attenuation in high port count optical line cards requiring independent timing domains.
CKIN1P_A
CKIN1N_A
CKIN1P_B
CKIN1N_B
CKIN1P_C
CKIN1N_C
CKIN1P_D
CKIN1N_D
RSTL_q
CS_q
Input Stage PLL Bypass
Synthesis Stage
Output Stage
÷ N31
Input
Monitor
÷ N32
f3
DSPLL^®
fOSC
A
÷ NC1_HS
PLL Bypass
÷ NC1
PLL Bypass
÷ N2
÷ N31
Input
Monitor
÷ N32
f3
DSPLL^®
fOSC
B
÷ NC1_HS
PLL Bypass
÷ NC1
PLL Bypass
÷ N2
÷ N31
Input
Monitor
÷ N32
f3
DSPLL^®
fOSC
÷ NC1_HS
C
PLL Bypass
÷ NC1
PLL Bypass
÷ N2
÷ N31
Input
Monitor
f3
DSPLL^®
fOSC
PLL Bypass
÷ NC1_HS
÷ NC1
D
÷ N32
÷ N2
Status / Control
High PSRR
Voltage Regulator
SCL SDA LOL_q IRQ_q
OSC_P/N
Low Jitter
XO or Clock
Figure 16. Si5375 Functional Block Diagram
CKOUT1P_A
CKOUT1N_A
CKOUT1P_B
CKOUT1N_B
CKOUT1P_C
CKOUT1N_C
CKOUT1P_D
CKOUT1N_D
VDD_q
GND
Rev. 1.2
31