SI5325C-C-GM Datasheet, PDF (38/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

Si53xx-RM
The Si5316 can accept a CKIN1 input at a different frequency than the CKIN2 input. The frequency of one input
clock can be 1x, 4x, or 32x the frequency of the other input clock. The output frequency is always equal to the lower
of the two clock inputs and is set via the FRQSEL [1:0] pins. The frequency applied at each clock input is divided
down by a pre-divider as shown in the Figure 1 on page 16. These pre-dividers must be set such that the two
resulting clock frequencies, f3_1 and f3_2 must be equal and are set by the FRQSEL [1:0] pins. Input divider
settings are controlled by the CK1DIV and CK2DIV pins, as shown in Table 5.
Table 5. Input Divider Settings
CKnDIV
L
M
H
N3n Input Divider
1
4
32
Table 6. Si5316 Bandwidth Values
BW[1:0]
HM
HL
FRQSEL[1:0] Nominal Frequency Values (MHz)
LL
LM
LH
ML
MM
MH
19.44 MHz 38.88 MHz 77.76 MHz 155.52 MHz 311.04 MHz 622.08 MHz
100 Hz
100 Hz
100 Hz
100 Hz
100 Hz
100 Hz
210 Hz
210 Hz
200 Hz
200 Hz
200 Hz
200 Hz
MH
410 Hz
410 Hz
400 Hz
400 Hz
400 Hz
400 Hz
MM
1.7 kHz
1.7 kHz
1.6 kHz
1.6 kHz
1.6 kHz
1.6 kHz
ML
7.0 kHz
7.0 kHz
6.8 kHz
6.7 kHz
6.7 kHz
6.7 kHz
CKIN1
CKIN2
 1,  4,  32
One-to-one
frequency ratio
f_{3 DSPLL Fout}
 1,  4,  32
f₃ = F_out
Figure 22. Si5316 Divisor Ratios
38
Rev. 1.2