SI5325C-C-GM Datasheet, PDF (172/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

Si53xx-RM
Si5374/75/76 Register Map Partition Example
In a typical line card application, an Si5374/75/76 will supply four clocks to four different channels that might need
to support any combination of services. For example, say that each of the four DSPLLs (A, B, C or D) can be
programmed for either a SONET, OTN/OTU or Ethernet frequency plan in any combination. In this example, call
the SONET plan P1, the OTN/OTU plan P2 and the Ethernet plan P3. Further, assume that there is a need for
dynamic allocation of services at run time. To avoid crosstalk between DSPLLs programmed with similar services
which may have operating frequencies that are close but not exactly the same, the following procedure is
suggested:
Run Si537xDSPLLsim three times, once each for OTN/OTU, Ethernet and SONET. This will result in three register
maps that are each comprised of four sub-maps A, B, C and D, as shown below:
Plan1:
SONET
Plan2:
OT N/OT U
Plan3:
Ethernet
P1A
P2A
P3A
P1B
P2B
P3B
P1C
P2C
P3C
P1D
P2D
P4D
Figure 106. Example Frequency Plan Sources
To accommodate a combination of the three different services at run time, the individual sub-maps from the three
different frequency plans can be placed into the four DSPLLs. However, it is recommended that DSPLL_A only be
loaded with a sub-map that was created for DSPLL_A and not with a sub-map created for any of the other three
DSPLLs, as shown below:
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