SI5325C-C-GM Datasheet, PDF (115/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

Si53xx-RM
Figure 63 shows similar results and ties them to RMS jitter values. It also helps to illustrate one potential remedy
for solutions with low f3. Note that 38.88 MHz x 5 = 194.4 MHz. In this case, an FPGA was used to multiply a
38.88 MHz input clock up by a factor of five to 194.4 MHz, using a feature such as the Xilinx DCM (Digital Clock
Manager). Even though FPGAs are notorious for having jittered outputs, the jitter attenuating feature of the
Narrowband Any-Frequency Clocks allow an FPGA’s output to be used to produce a very clean clock, as can be
seen from the jitter numbers below.
38.88 MHz in, 194.4 MHz in, 690.57 MHz out
0
-20
-40
-60
-80
-100
-120
-140
-160
10
100
1000
10000 100000 1000000 10000000 100000000
Offset Frequency (Hz)
Dark blue—38.88 MHz in, f3 = 3.214 kHz
Light blue—194.4 MHz in, f3 = 16.1 kHz
Figure 63. Jitter vs. f3 with FPGA
Table 53. Jitter Values for Figure 63
Jitter Bandwidth
OC-48, 12 kHz to 20 MHz
OC-192, 20 kHz to 80 MHz
OC-192, 4 MHz to 80 MHz
OC-192, 50 kHz to 80 MHz
800 Hz to 80 MHz
f3 = 3.214 kHz
CKIN = 38.88 MHz
Jitter, RMS
1,034 fs
668 fs
169 fs
374 fs
3,598 fs
f3 = 16.1 kHz
CKIN = 194.4 MHz
Jitter, RMS
285 fs
300 fs
168 fs
287 fs
378 fs
Rev. 1.2
115