SI5325C-C-GM Datasheet, PDF(59/178 Page) Silicon Laboratories

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SI5325C-C-GM Datasheet, PDF (59/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

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Si53xx-RM

5.6.5. Disabling FS_OUT (Si5366)

The FS_OUT maybe disabled via the DBLFS pin, see Table 20. The additional state (M) provided allows for

FS_OUT to drive a CMOS load while the other clock outputs use a different signal format as specified by the

SFOUT[1:0] pins.

Table 20. FS_OUT Disable Control (DBLFS)

DBLFS

FS_OUT State

Tri-State/Powerdown

Active/CMOS Format

Active/SFOUT[1:0] Format

5.7. Output Clock Drivers

The devices include a flexible output driver structure that can drive a variety of loads, including LVPECL, LVDS,

CML, and CMOS formats. The signal format is selected jointly for all outputs using the SFOUT [1:0] pins, which

modify the output common mode and differential signal swing. See the appropriate data sheet for output driver

specifications. The SFOUT [1:0] pins are three-level input pins, with the states designated as L (ground), M (VDD/

2), and H (VDD).

Table 21 shows the signal formats based on the supply voltage and the type of load being driven. For the CMOS

setting (SFOUT = LH), both output pins drive single-ended in-phase signals and should be externally shorted

together to obtain the drive strength specified in the data sheet.

Table 21. Output Signal Format Selection (SFOUT)

SFOUT[1:0]

All Others

Signal Format

CML

LVDS

CMOS

Disabled

LVPECL

Low-swing LVDS

Reserved

The SFOUT [1:0] pins can also be used to disable the output. Disabling the output puts the CKOUT+ and CKOUTâ

pins in a high-impedance state relative to VDD (common mode tri-state) while the two outputs remain connected to

each other through a 200 ï on-chip resistance (differential impedance of 200 ï). The maximum amount of internal

circuitry is powered down, minimizing power consumption and noise generation. Changing SFOUT without a reset

causes the output to output skew to become random. When SFOUT = LH for CMOS, PLL bypass mode is not

supported.

5.7.1. LVPECL and CMOS TQFP Output Signal Format Restrictions at 3.3 V (Si5365, Si5366)

The LVPECL and CMOS output formats draw more current than either LVDS or CML. However, the allowed output

format pin settings are restricted so that the maximum power dissipation for the TQFP devices is limited when they

are operated at 3.3 V. When SFOUT[1:0] = MH or LH (for either LVPECL or CMOS), either DBL5 must be H or

DBL34 must be high.

Rev. 1.2

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