SI5325C-C-GM Datasheet, PDF (65/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

Si53xx-RM
Xtal, or Refclock
(Si5319, Si5324, Si5326, Si5327, Si5368, Si5369;
Refclock only for the Si5374, Si5375, and Si5376)
CKIN_1+
2
÷ N31
CKIN_1–
CKIN_2+
2
÷ N32
CKIN_2–
Si5368
Si5369
CKIN_3+
CKIN_3–
CKIN_4+
CKIN_4–
2
÷ N33
2
÷ N34
BYPASS
1
fx
÷ NC1
0
f3
Digital
Phase
Detector/
M
DCO ^fOSC ÷ N1_HS
÷ NC2
1
f3 ^{Loop Filter}
0
÷ N2_LS ÷ N2_HS
Si5368
Si5369
÷ NC3
1
0
÷ NC4
1
0
2 CKOUT_1+
CKOUT_1–
2 CKOUT_2+
CKOUT_2–
2 CKOUT_3+
CKOUT_3–
2 CKOUT_4+
CKOUT_4–
SPI/I²C
Si5319, Si5326,
Si5368
Control
Bandwidth
Control
FSYNC
(Si5368)
1
÷ NC5
2
0
Note: See section 6.7
for FSYNC details.
CKOUT_5+
CKOUT_5–
Note: There are multiple outputs at different frequencies because of limitations caused by the DCO and N1_HS.
Figure 24. Narrowband PLL Divider Settings
(Si5319, Si5324, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, Si5375, and Si5376)
Table 26. Narrowband Frequency Limits
Signal
Frequency Limits
CKINn
2 kHz–710 MHz
f₃
2 kHz–2 MHz
f_OSC
4.85–5.67 GHz
f_OUT
2 kHz–1.475 GHz
Note: Fmax = 346 MHz for the Si5328 and 808 MHz for the
Si5327, Si5374, Si5375, and Si5376. Each entry has
500 ppm margins at both ends. The Si5374, Si5375, and
Si5376 have an extend Fosc range of from 4.6 to 6 GHz.
Divider
Equation
N1 N1 = N1_HS x NCn_LS
N2 N2 = N2_HS x N2_LS
N3 N3 = N3n
Table 27. Dividers and Limits
Si5325, Si5367
N1_HS = [4, 5, …, 11]
NCn_LS = [1, 2, 4, 6, …, 2²⁰]
N2_HS = 1
N2_LS = [32, 34, 36, …, 2⁹]
N3n = [1,2,3,..,2¹⁹]
Si5319, Si5324, Si5326, Si5327,
Si5328, Si5368, Si5369, Si5374,
Si5375, Si5376
N1_HS = [4, 5, …, 11]
NCn_LS = [1, 2, 4, 6, …, 2²⁰]
N2_HS = [4, 5, …, 11]
N2_LS = [2, 4, 6, …, 2²⁰]
N3n = [1,2,3,..,2¹⁹]
Rev. 1.2
65