SI5325C-C-GM Datasheet, PDF (36/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

Si53xx-RM
4.2.3. Jitter Tolerance
Jitter tolerance is defined as the maximum peak-to-peak sinusoidal jitter that can be present on the incoming clock
before the DSPLL loses lock. The tolerance is a function of the jitter frequency, because tolerance improves for
lower input jitter frequency.
The jitter tolerance of the DSPLL is a function of the loop bandwidth setting. Figure 21 shows the general shape of
the jitter tolerance curve versus input jitter frequency. For jitter frequencies above the loop bandwidth, the tolerance
is a constant value A_j0. Beginning at the PLL bandwidth, the tolerance increases at a rate of 20 dB/decade for
lower input jitter frequencies.
Input
Jitter
Amplitude
A_j0
–20 dB/dec.
Excessive Input Jitter Range
BW/100 BW/10 BW
f_{Jitter In}
Figure 21. Jitter Tolerance Mask/Template
The equation for the high frequency jitter tolerance can be expressed as a function of the PLL loop bandwidth (i.e.,
bandwidth):
A_j0
=
5_----0_---0_----0_-
BW
ns pk-pk
For example, the jitter tolerance when f_in = 155.52 MHz, f_out = 622.08 MHz and the loop bandwidth (BW) is 100 Hz:
A_j0
=
5_----0_---0_---0_--
100
=
50 ns pk-pk
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Rev. 1.2