SI5325C-C-GM Datasheet, PDF (22/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

Si53xx-RM
3.7. Si5326
The Si5326 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance.
The Si5326 accepts dual clock inputs ranging from 2 kHz to 710 MHz and generates two independent,
synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides
virtually any frequency translation combination across this operating range. The Si5326 input clock frequency and
clock multiplication ratios are programmable through an I²C or SPI interface. The DSPLL loop bandwidth is digitally
programmable from 60 Hz to 8 kHz, providing jitter performance optimization at the application level. Operating
from a single 1.8, 2.5, or 3.3 V supply, the Si5326 is ideal for providing clock multiplication and jitter attenuation in
high-performance timing applications. See "6. Microprocessor Controlled Parts (Si5319, Si5324, Si5325, Si5326,
Si5327, Si5328, Si5367, Si5368, Si5369, Si5374, Si5375, and Si5376)" on page 63 for a complete description.
CKIN_1 + ²
CKIN_1 –
CKIN_2 + ²
CKIN_2 –
÷ N31
÷ N32
0
1
0 _f3
1
INT_C1B
C2B
Signal
Detect
LOL
CS_CA
CMODE
SDA_SDO
SCL
SDI
A[2]/SS
A[1:0]
INC
DEC
RST
Control
Xtal or Refclock
RATE[1:0]
XB
XA
3
DSPLL
BYPASS
DSPLL^®
÷ N2
fOSC _{÷ NC1}
1
0
÷ N1_HS
1
÷ NC2
0
2/
CKOUT_1 +
CKOUT_1 –
2
CKOUT_2 +
CKOUT_2 –
VDD
GND
Figure 7. Si5326 Clock Multiplier and Jitter Attenuator Block Diagram
22
Rev. 1.2