SI5325C-C-GM Datasheet, PDF (54/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

Si53xx-RM
5.3. Pin Control Input Clock Control
This section describes the clock selection capabilities (manual input selection, automatic input selection, hitless
switching, and revertive switching). When switching between two clocks, LOL may temporarily go high if the two
clocks differ in frequency by more than 100 ppm.
5.3.1. Manual Clock Selection
Manual control of input clock selection is chosen via the CS[1:0] pins according to Table 13 and Table 14.
Table 13. Manual Input Clock Selection (Si5316, Si5322, Si5323), AUTOSEL = L
CS (Si5316)
CS_CA (Si5322, Si5323)
0
1
Si5316
Si5322
CKIN1
CKIN2
Si5323
The manual input clock selection settings for the Si5365 and the Si5366 are shown in Table 14. The Si5366 has
two modes of operation (See Section “5.5. Frame Synchronization (Si5366)”). With CK_CONF = 0, any of the four
input clocks may be selected manually; however, when CK_CONF = 1 the inputs are paired, CKIN1 is paired with
CKIN3 and likewise for CKIN2 and CKIN4. Therefore, only two settings are available to select one of the two pairs.
Table 14. Manual Input Clock Selection (Si5365, Si5366), AUTOSEL = L
[CS1_CA4, CS0_CA3]_Pins Si5365
00
CKIN1
01
CKIN2
10
CKIN3
11
CKIN4
Si5366
CK_CONF = 0
CK_CONF = 1
(5 Output Clocks) (FS_OUT Configuration)
CKIN1
CKIN1/CKIN3
CKIN2
CKIN2/CKIN4
CKIN3
Reserved
CKIN4
Reserved
Notes:
1. To avoid clock switching based on intermediate states during a CS state change, the CS input pins are
internally deglitched.
2. If the selected clock enters an alarm condition, the PLL enters digital hold mode.
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Rev. 1.2