SI5325C-C-GM Datasheet, PDF (18/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

Si53xx-RM
3.3. Si5322
The Si5322 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter
attenuation. The Si5322 accepts dual clock inputs ranging from 19.44 to 707 MHz and generates two frequency-
multiplied clock outputs ranging from 19.44 to 1050 MHz. The input clock frequency and clock multiplication ratio
are selectable from a table of popular SONET, Ethernet, Fibre Channel, and broadcast video (HD SDI, 3G SDI)
rates. The DSPLL loop bandwidth is digitally selectable from 150 kHz to 1.3 MHz. Operating from a single 1.8, 2.5,
or 3.3 V supply, the Si5322 is ideal for providing low jitter clock multiplication in high performance timing
applications. See "5. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)" on page 37 for a complete
description.
CKIN_1+
2
CKIN_1–
CKIN_2+
2
CKIN_2–
0
f3
1
C1B
Signal
C2B
Detect
DSPLL^®
0
fOSC
1
0
1
2
CKOUT_1+
CKOUT_2–
SFOUT[1:0]
2
CKOUT_2+
CKOUT_2–
DBL2_BY
AUTOSEL
CS_CA
BWSEL[1:0]
FRQTBL
FRQSEL[3:0]
RST
Bandwidth
Control
Control
Frequency
Control
VDD
GND
Figure 3. Si5322 Low Jitter Clock Multiplier Block Diagram
Note: Not recommended for new designs. For alternatives, see the Si533x family of products.
18
Rev. 1.2