SI5325C-C-GM Datasheet, PDF (171/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

Si53xx-RM
Figure 105. Si5374, Si5375, and Si5376 DSPLL D
Because they contain four different and independent DSPLLs, the Si5374, Si5375, and Si5376 are supported by a
different software called Si537xDSLLsim. Noting that applications may be plesiochronous, the VCOs of the
DSPLLs can be very close in frequency to one another, which results in crosstalk susceptibility.
To minimize VCO crosstalk, Si537xDSPLLsim is aware that, for almost all frequency plans, there is more than one
possible VCO value. Si537xDSPLLsim makes use of this and strategically places frequency plans in DSPLL
locations so that DSPLLs that are next to one another will not have the same VCO value. For example, there are
two possible VCO values for a 622.08 MHz clock output frequency. In this case, DSPLLs A and C would have one
VCO value, while DSPLLs B and D would have a different VCO value. In this way, DSPLLs that are diagonally
opposite will have the same VCO value, but immediately adjacent DSPLLs will have different VCO values. In
general, the lower the output frequency, the greater the number of potential VCO values. With output frequencies
less than 200 MHz, there are usually four difference VCO values, which means that all four DSPLLs can have their
own unique VCO value.
To further minimize crosstalk, Si537xDSPLLsim automatically initializes the four DSPLLs with Free Run frequency
plans that both separate and pre-place the four VCO values. This ensures that they will not interfere with each
other or with any subsequent entered frequency plans.
Rev. 1.2
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