SI5325C-C-GM Datasheet, PDF (27/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

Si53xx-RM
3.12. Si5367
The Si5367 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter
attenuation. The Si5367 accepts four clock inputs ranging from 10 to 707 MHz and generates five frequency-
multiplied clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The Si5367 input clock
frequency and clock multiplication ratio are programmable through an I²C or SPI interface. The DSPLL loop
bandwidth is digitally programmable from 150 kHz to 1.3 MHz. Operating from a single 1.8, 2.5, or 3.3 V supply, the
Si5367 is ideal for providing clock multiplication in high performance timing applications. See "6. Microprocessor
Controlled Parts (Si5319, Si5324, Si5325, Si5326, Si5327, Si5328, Si5367, Si5368, Si5369, Si5374, Si5375, and
Si5376)" on page 63 for a complete description.
CKIN_1+ 2
CKIN_1–
CKIN_2+ 2
CKIN_2–
CKIN_3+ 2
CKIN_3–
CKIN_4+ 2
CKIN_4–
÷ N3_1
÷ N3_2
÷ N3_3
÷ N3_4
C1B
C2B
C3B
INT_ALM
C1A
C2A
CS0_C3A
CS1_C4A
f3
DSPLL^®
÷ N2
Control
fOSC
÷ N1_HS
3
1
÷ NC1
0
1
÷ NC2
0
1
÷ NC3
0
÷ NC4
1
0
÷ NC5
1
0
BYPASS/DSBL2
2 CKOUT_1+
CKOUT_1–
2 CKOUT_2+
CKOUT_2–
DSBL2/BYPASS
2 CKOUT_3+
CKOUT_3–
DSBL34
2 CKOUT_4+
CKOUT_4–
2 CKOUT_5+
CKOUT_5–
DSBL5
VDD
GND
Figure 12. Si5367 Clock Multiplier Block Diagram
Note: Not recommended for new designs. For alternatives, see the Si53xx family of products.
Rev. 1.2
27