SI5325C-C-GM Datasheet, PDF (63/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

Si53xx-RM
6. Microprocessor Controlled Parts (Si5319, Si5324, Si5325, Si5326, Si5327,
Si5328, Si5367, Si5368, Si5369, Si5374, Si5375, and Si5376)
The devices in this family provide a rich set of clock multiplication/clock division options, loop bandwidth selections,
output clock phase adjustment, and device control options.
6.1. Clock Multiplication
The input frequency, clock multiplication ratio, and output frequency are set via register settings. Because the
DSPLL dividers settings are directly programmable, a wide range of frequency translations is available. In addition,
a wider range of frequency translations is available in narrowband parts than wideband parts due to the lower
phase detector frequency range in narrowband parts. To assist users in finding valid divider settings for a particular
input frequency and clock multiplication ratio, Silicon Laboratories offers the DSPLLsim utility to calculate these
settings automatically. When multiple divider combinations produce the same output frequency, the software
recommends the divider settings that yield the best combination of phase noise performance and power
consumption.
6.1.1. Jitter Tolerance (Si5319, Si5324, Si5325, Si5326, Si5327, Si5328, Si5368, Si5369, Si5374, Si5375, and
Si5376)
See "4.2.3. Jitter Tolerance" on page 36.
6.1.2. Wideband Parts (Si5325, Si5367)
These devices operate as wideband clock multipliers without an external resonator or reference clock. This mode
may be desirable if the input clock is already low jitter and only simple clock multiplication is required. A limited
selection of clock multiplication factors is available in this mode. The input-to-output skew for wideband parts is not
controlled.
Refer to Figure 23. The selected input clock passes through the N3 input divider and is provided to the DSPLL. The
input-to-output clock multiplication ratio is defined as follows:
f_OUT = f_IN x N2/(N1 x N3)
where:
N1 = output divider
N2 = feedback divider
N3 = input divider
f_IN = 10 MHz–710 MHz
CKIN1
/
2
CKIN2
/
2
N31
N32
f3
10 MHz–
157.5 MHz
DSPLL^®
4.85 – 5.67 GHz
fOSC
N1_HS
f_OUT = 2 kHz-–1. 4 GHz
N1
NC1 / CKOUT_1
2
NC2 / CKOUT_2
2
CKIN3
CKIN4
/
N33
2
N2
f3
N 2 = N2_LS
N2_LS = [32, 34, 36, …, 512]
/
N34
2
N3 =
[1,2,3,...,2¹⁹]
NC5 /
2
NC1 = N1_ HS x N1_LS
N1_ HS= [4,5,6,...,11]
N1_ LS= [1,2,4,6,...,2²⁰]
CKOUT_5
Figure 23. Wideband PLL Divider Settings (Si5325, Si5367)
Rev. 1.2
63