SI5325C-C-GM Datasheet, PDF (163/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

Si53xx-RM
APPENDIX J—Si5374, Si5375, Si5376 PCB LAYOUT RECOMMENDATIONS
The following is a set of recommendations and guidelines for printed circuit board layout with the Si5374, Si5375,
and Si5376 devices. Because the four DSPLLs are in close physical and electrical proximity to one another, PCB
layout is critical to achieving the highest levels of jitter performance. The following images were taken from the
Si537x-EVB (evaluation board) layout. For more details about this board, refer to the Si537x-EVB Evaluation Board
User's Guide.
Isolated Vdd’s
Main Vdd
Isolated Vdd’s
The four Vdd supplies should be isolated from one another with four ferrite beads. They should be
separately bypassed with capacitors that are located very close to the Si537x device.
Figure 98. Vdd Plane
 Use a solid and undisturbed ground plane for the Si537x and all of the clock input and output return paths.
 For applications that wish to logically connect the four RSTL_x signals, do not tie them together underneath the
BGA package. Instead connect them outside of the BGA footprint.
 Where possible, place the CKOUT and CKIN signals on separate PCB layers with a ground layer between
them. The use of ground guard traces between all clock inputs and outputs is recommended.
Rev. 1.2
163