SI5325C-C-GM Datasheet, PDF (164/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

Si53xx-RM
These four resistors force the common RESET connection away from the BGA footprint
Figure 99. Ground Plane and Reset
RSTL_x Pins
It is highly recommended that the four RSTL_x pins (RSTL_A, RSTL_B, RSTL_C and RSTL_D) be logically
connected to one another so that the four DSPLLs are always either all in reset or are all out of reset. While in
reset, the DSPLLs VCO will continue to run, and, because the VCOs will not be locked to any signal, they will drift
and can be any frequency value within the VCO range. If a drifting VCO happens to have a frequency value that is
close to an operational DSPLLs VCO, there could be crosstalk between the two VCOs. To avoid this issue, Si537x
DSPLLsim initializes the four DSPLLs with default Free Run frequency plans so that the VCO values are apart from
one another. If the four RSTL_x pins are directly connected to one another, the connections should not occur
directly underneath the BGA package. Instead, the connections should occur outside of the package footprint.
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Rev. 1.2