SI5325C-C-GM Datasheet, PDF (28/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

Si53xx-RM
3.13. Si5368
The Si5368 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter
performance. The Si5368 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five
independent, synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The
device provides virtually any frequency translation combination across this operating range. The Si5368 input clock
frequency and clock multiplication ratio are programmable through an I²C or SPI interface. The DSPLL loop
bandwidth is digitally programmable from 60 Hz to 8 kHz, providing jitter performance optimization at the
application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5368 is ideal for providing clock
multiplication and jitter attenuation in high performance timing applications. See "6. Microprocessor Controlled
Parts (Si5319, Si5324, Si5325, Si5326, Si5327, Si5328, Si5367, Si5368, Si5369, Si5374, Si5375, and Si5376)" on
page 63 for a complete description.
RATE[1:0] ^{Xtal or Refclock}
XB
XA
CKIN_1+ 2
CKIN_1–
÷ N3_1
CKIN_2+ ₂
CKIN_2–
÷ N3_2
f3
CKIN_3+ 2
CKIN_3–
÷ N3_3
CKIN_4+ 2
CKIN_4–
÷ N3_4
C1B
C2B
C3B
INT_ALM
C1A
C2A
CS0_C3A
CS1_C4A
LOL
Control
DSPLL^®
fx
fOSC
÷ N1_HS
÷ N2
CKOUT_2
CKIN_3
CKIN_4
FSYNC
FSYNC
LOGIC/
ALIGN
3
1
÷ NC1
0
1
÷ NC2
0
1
÷ NC3
0
÷ NC4
1
0
÷ NC5
1
0
BYPASS/DSBL2
2 CKOUT_1+
CKOUT_1–
2 CKOUT_2+
CKOUT_2–
DSBL2/BYPASS
2 CKOUT_3+
CKOUT_3–
DSBL34
2 CKOUT_4+
CKOUT_4–
2 CKOUT_5+
CKOUT_5–
DSBL5
VDD
GND
Figure 13. Si5368 Clock Multiplier and Jitter Attenuator Block Diagram
28
Rev. 1.2