SI5325C-C-GM Datasheet, PDF (30/178 Pages) Silicon Laboratories – ANY-FREQUENCY PRECISION CLOCKS

Si53xx-RM
3.16. Si5374
The Si5374 is a highly integrated, 4-PLL jitter-attenuating precision clock multiplier for applications requiring sub 1
ps jitter performance. Each of the DSPLL® clock multiplier engines accepts two input clocks ranging from 2 kHz to
710 MHz and generates two independent, synchronous output clocks ranging from 2 kHz to 808 MHz. Each
DSPLL provides virtually any frequency translation across this operating range. For asynchronous, free-running
clock generation applications, the Si5374’s reference oscillator can be used as a clock source for the four DSPLLs.
The Si5374 input clock frequency and clock multiplication ratio are programmable through an I2C interface. The
Si5374 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-frequency
synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and
loop filter components. Each DSPLL loop bandwidth is digitally programmable from 4 to 525 Hz, providing jitter
performance optimization at the application level. The device operates from a single 1.8 or 2.5 V supply with on-
chip voltage regulators with excellent PSRR. The Si5374 is ideal for providing clock multiplication and jitter
attenuation in high port count optical line cards requiring independent timing domains.
CKIN1P_A
CKIN1N_A
CKIN2P_A
CKIN2N_A
Internal
Osc
CKIN3P_B
CKIN3N_B
CKIN4P_B
CKIN4N_B
Internal
Osc
CKIN5P_C
CKIN5N_C
CKIN6P_C
CKIN6N_C
Internal
Osc
CKIN7P_D
CKIN7N_D
CKIN8P_D
CKIN8N_D
Internal
Osc
Input Stage PLL Bypass
÷ N31
Input
Monitor
f3
÷ N32
Hitless
Switch
PLL Bypass
÷ N31
Input
Monitor
f3
÷ N32
Hitless
Switch
PLL Bypass
÷ N31
Input
Monitor
f3
÷ N32
Hitless
Switch
PLL Bypass
÷ N31
Input
Monitor
f3
÷ N32
Hitless
Switch
Synthesis Stage
DSPLL^®
A
fOSC
÷ NC1_HS
÷ N2
DSPLL^®
B
fOSC
÷ NC1_HS
÷ N2
DSPLL^®
C
fOSC
÷ NC1_HS
÷ N2
DSPLL^®
D
fOSC
÷ NC1_HS
÷ N2
Output Stage
PLL Bypass
÷ NC1
÷ NC2
PLL Bypass
PLL Bypass
÷ NC1
÷ NC2
PLL Bypass
PLL Bypass
÷ NC1
÷ NC2
PLL Bypass
PLL Bypass
÷ NC1
÷ NC2
PLL Bypass
RSTL_q
CS_q
Status / Control
High PSRR
Voltage Regulator
SCL SDA LOL_q IRQ_q
OSC_P/N
Low Jitter
XO or Clock
Figure 15. Si5374 Functional Block Diagram
CKOUT1P_A
CKOUT1N_A
CKOUT2P_A
CKOUT2N_A
CKOUT3P_B
CKOUT3N_B
CKOUT4P_B
CKOUT4N_B
CKOUT5P_C
CKOUT5N_C
CKOUT6P_C
CKOUT6N_C
CKOUT7P_D
CKOUT7N_D
CKOUT8P_D
CKOUT8N_D
VDD_q
GND
30
Rev. 1.2