SI5380_16 Datasheet, PDF (9/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Rev D Data Sheet
Functional Description
3.2 External Reference (XA/XB)
An external crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra-low phase noise reference clock
for the DSPLL and for providing a stable reference for the free-run and holdover modes. A simplified diagram is shown in the figure
below. The Si5380 includes internal XTAL loading capacitors which eliminates the need for external capacitors and also has the benefit
of reduced noise coupling from external sources. Refer to the Table 5.12 Crystal Specifications on page 34 for crystal specifications.
A crystal frequency of 54 MHz is required, with a total accuracy of ±100 ppm* recommended for best performance. The Si5380 includes
built-in XTAL load capacitors (C_L) of 8 pF, which are switched out of the circuit when using an external XO. The Si5380 Reference
Manual provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance. To ach-
ieve optimal jitter performance and minimize BOM cost, a crystal is recommended on the XA/XB reference input. A clock (e.g., XO) may
be used in lieu of the crystal, but it may result in higher output jitter. See the Si5380 Reference Manual for more information. Selection
between the external XTAL or REFCLK is controlled by register configuration. The internal crystal loading capacitors (C_L) are disabled
in this mode. It is important to note that when using the REFCLK option the phase noise of the outputs is directly affected by the phase
noise of the external XO reference. Refer to the Table 5.3 Input Clock Specifications on page 24 for REFCLK requirements when
using the REFCLK mode.
Note: Including initial frequency tolerance and frequency variation over the full operating temperature range, voltage range, load condi-
tions, and aging.
54MHz
XO
54MHz
XO
54MHz
XTAL
XA
XB
2xCL
OSC
2xCL
÷PREF
100
XA
XB
2xCL
OSC
2xCL
÷PREF
XA
XB
2xCL
OSC
2xCL
÷PREF
Si5380
Crystal Resonator Connection
Si5380
Differential XO Connection
Si5380
Single-Ended XO Connection
Figure 3.4. XAXB Crystal Resonator and External Reference Clock Connection Options
3.3 Inputs (IN0, IN1, IN2, IN3/FB_IN)
Four clock inputs are available to synchronize the DSPLL. The inputs are compatible with both single-ended and differential signals.
Input selection can be manual (pin or register controlled) or automatic with definable priorities.
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