SI5380_16 Datasheet, PDF (27/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Rev D Data Sheet
Electrical Specifications
Parameter
Output Frequency
Duty Cycle
Output-Output Skew
OUT-OUTb Skew
Output Voltage Amplitude ¹
Common Mode Voltage¹
Rise and Fall Times (20% to
80%)
Differential Output Impedance
Power Supply Noise Rejection ²
Output-Output Crosstalk³
Table 5.5. Differential Clock Output Specifications
Symbol
f_OUT
DC
T_SK
T_{SK_OUT}
V_OUT
V_CM
t_R/t_F
Test Condition
f ≤ 400 MHz
f > 400 MHz
Outputs at 737.28 MHz
connected to the same
"N-divider"
Outputs at 737.28 MHz
connected to different "N-di-
viders"
Measured from the positive
to negative output pins
V_DDO =
LVDS
3.3 V or
2.5 V or
1.8 V
V_DDO = 3.3 V
or 2.5 V
LVPECL
V_DDO =
3.3 V
LVDS
LVPECL
V_DDO =
2.5 V
LVPECL
LVDS
V_DDO =
sub-LVDS
1.8 V
Min
0.480
48
45
—
—
—
350
640
1.10
1.90
1.1
0.8
—
Z_O
—
PSRR
10 kHz sinusoidal noise
—
100 kHz sinusoidal noise
—
500 kHz sinusoidal noise
—
1 MHz sinusoidal noise
—
XTALK
Measured spur from adja-
—
cent output
Typ
—
—
—
—
—
0
430
750
1.2
2.0
1.2
0.9
100
100
–101
–96
–99
–97
–72
Max
1474.56
52
55
65
Unit
MHz
%
%
ps
90
ps
50
ps
510
mVpp_se
900
1.3
V
2.1
1.3
1.00
150
ps
—
Ω
—
dBc
—
dBc
—
dBc
—
dBc
—
dB
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