SI5380_16 Datasheet, PDF (45/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Rev D Data Sheet
Pin Description
Pin Name
Pin Number
Pin Type¹
Function
VDDO0
22
VDDO1
26
VDDO2
29
VDDO3
33
VDDO4
36
VDDO5
40
P
Output Clock Supply Voltage. Supply voltage (3.3 V, 2.5
V, 1.8 V) for OUTx, OUTxb Outputs. Note that VDDO0
P
supplies power to OUT0 and OUT0A; VDDO9 supplies
P
power to OUT9 and OUT9A. Leave VDDO pins of unused
output drivers unconnected. An alternative option is to con-
P
nect the VDDO pin to a power supply and disable the output
driver to minimize current consumption. A 1 µF bypass ca-
P
pacitor should be placed very close to each connected
P
VDDO pin.
VDDO6
43
P
VDDO7
49
P
VDDO8
52
P
VDDO9
57
P
GND PAD
P
Ground Pad. This pad provides connection to ground and
must be connected for proper operation.
Note:
1. I = Input, O = Output, P = Power
2. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
3. All status pins except I2C and SPI are push-pull.
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