SI5380_16 Datasheet, PDF (42/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Pin Name
XA
XB
X1
X2
IN0
IN0b
IN1
IN1b
IN2
IN2b
IN3/FB_IN
IN3b/FB_INb
Outputs
Pin Number
8
9
7
10
63
64
1
2
14
15
61
62
Si5380 Rev D Data Sheet
Pin Description
Table 9.1. Pin Descriptions
Pin Type¹
I
I
I
I
I
I
I
I
I
I
I
I
Function
Crystal Input. Input pin for external crystal (XTAL). Alterna-
tively these pins can be driven with an external reference
clock (REFCLK). An internal register bit selects XTAL or
REFCLK mode. Default is XTAL mode. Single-ended inputs
must be connected to the XA pin, with the XB pin appropri-
ately terminated.
XTAL Shield. Connect these pins directly to the crystal
ground pins. Both the X1/X2 pins and Crystal ground pins
should be separated from the PCB ground plane. Refer to
the Reference Manual for layout guidelines.
Clock Inputs. These pins accept an input clock for syn-
chronizing the device. They support both differential and
single-ended clock signals. Refer to 3.3.1 Input Configura-
tion and Terminations for input termination options. These
pins are high-impedance and must be terminated externally,
when being used. The negative side of the differential input
must be ac-grounded when accepting a single-ended clock.
Unused inputs may be left unconnected.
Clock Input 3/External Feedback Input.
By default, these pins are used as the 4^th clock input (IN3/
IN3b). They can also be used as the external feedback in-
put (FB_IN/FB_INb) for the optional zero delay mode. See
section 5.3.6 for details on the optional zero delay mode.
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