SI5380_16 Datasheet, PDF (24/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Rev D Data Sheet
Electrical Specifications
Table 5.2. DC Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Core Supply Current ^1,2
I_DD
—
190
310
mA
I_DDA
—
125
135
mA
Output Buffer Supply Current ^{2, 5}
I_DDO
LVPECL Output ³
—
36
41
mA
@ 1474.56 MHz
LVPECL Output ³
—
22
26
mA
@ 153.6 MHz
LVDS Output ³
—
25
29
mA
@ 1474.56 MHz
LVDS Output ³
—
15
18
mA
@ 153.6 MHz
3.3 V LVCMOS Output ⁴
—
22
30
mA
@ 153.6 MHz
2.5 V LVCMOS Output ⁴
—
18
23
mA
@ 153.6 MHz
1.8 V LVCMOS Output ⁴
—
12
16
mA
@ 153.6 MHz
Total Power Dissipation ^{1, 2}
P_d
Typical Outputs
—
1300
1600
mW
Notes:
1. Si5380 test configuration: 3 × 3.3 V LVPECL outputs enabled at 122.88 MHz, 2 × 3.3 V LVPECL outputs enabled at 491.52 MHz,
1 × 3.3 V LVPECL output enabled at 983.04 MHz. Excludes power in termination resistors.
2. Detailed power consumption for any configuration can be estimated using ClockBuilder Pro when an evaluation board (EVB) is
not available. All EVBs support detailed current measurements for any configuration.
3. Differential outputs terminated into an ac-coupled 100 Ω load.
4. LVCMOS outputs measured into a 5-inch 50 Ω PCB trace with 5 pF load. The LVCMOS outputs were set to
OUTx_CMOS_DRV=3, which is the strongest driver setting. Refer to the Si5380 Reference Manual for more details on register
settings.
5. VDDO0 supplies power to both OUT0 and OUT0A buffers. Similarly, VDDO9 supplies power to both OUT9 and OUT9A buffers.
Differential Output Test Configuration
LVCMOS Output Test Configuration
IDDO
OUT
OUTb
0.1 uF
50
IDDO
Trace length 5
inches
50
499 Ω
0.1 uF
50 Ω Scope Input
100
OUT
OUTb
4.7 pF
56 Ω
50
0.1 uF
499 Ω
0.1 uF
50
50 Ω Scope Input
4.7 pF
56 Ω
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