SI5380_16 Datasheet, PDF (36/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Rev D Data Sheet
Electrical Specifications
Table 5.14. Absolute Maximum Ratings ^{1, 2, 3, 4}
Parameter
Symbol
Test Condition
Value
Unit
DC Supply Voltage
V_DD
–0.5 to 3.8
V
V_DDA
–0.5 to 3.8
V
V_DDO
–0.5 to 3.8
V
Input Voltage Range
V_I15
IN0-IN3/FB_IN
–0.85 to 3.8
V
V_I2
IN_SEL[1:0],
–0.5 to 3.8
RSTb, PDNb,OEb, SYNCb,
I2C_SEL, SCLK,
A0/CSb, A1/SDO,
SDA/SDIO
V_I3
XA/XB
–0.5 to 2.7
V
Latch-up Tolerance
LU
JESD78 Compliant
ESD Tolerance
HBM
100 pF, 1.5 kΩ
2.0
kV
Storage Temperature Range
T_STG
–55 to 150
°C
Max Junction Temperature in Operation
T_JCT
125
°C
Soldering Temperature (Pb-free profile) ⁴
T_PEAK
260
°C
Soldering Temperature Time at T_PEAK (Pb-
T_P
free profile) ⁴
20 to 40
sec
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
2. 64-QFN is RoHS-6 compliant.
3. For MSL rating and additional packaging information, go to http://www.silabs.com/support/quality/pages/RoHSInformation.aspx.
4. The device is compliant with JEDEC J-STD-020.
5. The minimum voltage at these pins can be as low as -1.0 V when an AC input signal is applied. See Table 5.3 Input Clock Speci-
fications on page 24 spec for Single-ended AC-coupled f_IN < 245.76 MHz.
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