SI5380_16 Datasheet, PDF (6/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

IN_SEL[1:0]
IN0
IN0b
IN1
IN1b
IN2
IN2b
IN3/FB_IN
IN3b/FB_INb
Si5380
÷P0
÷P1
DSPLL
÷P2
PD LPF
÷P3
÷M ÷5
Si5380 Rev D Data Sheet
Functional Description
÷N0 t0
÷R0A
÷R0
÷R5
÷R6
÷R7
÷R8
÷R9
÷R9A
÷N1 t1
÷R1
÷N2 t2
÷R2
÷N3 t3
÷R3
÷N4 t4
÷R4
VDDO0
OUT0A
OUT0Ab
OUT0
OUT0b
VDDO5
OUT5
OUT5b
VDDO6
OUT6
OUT6b
VDDO7
OUT7
OUT7b
VDDO8
OUT8
OUT8b
Device
Clocks
OUT9
OUT9b
OUT9A
OUT9Ab
VDDO9
VDDO1
OUT1
OUT1b
VDDO2
OUT2
OUT2b
VDDO3
OUT3
OUT3b
VDDO4
OUT4
OUT4b
SYSREF
Clocks
Figure 3.1. Example Divider Configuration for Generating JESD204B Subclass 1 Clocks
3.1.3 DSPLL Loop Bandwidth
The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register configurable DSPLL loop bandwidth set-
tings in the range of 0.1 Hz to 100 Hz are available for selection. The DSPLL will always remain stable with less than 0.1 dB of peaking
regardless of the DSPLL loop bandwidth selection.
3.1.4 Fastlock
Selecting a low DSPLL loop bandwidth (e.g., 1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting a
temporary fastlock loop bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will enable
the DSPLL to lock faster. Once lock acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL
Loop Bandwidth setting. Fastlock loop bandwidth settings in the range of 100 Hz to 4 kHz are available for selection. The fastlock fea-
ture can be enabled or disabled by register configuration.
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