SI5380_16 Datasheet, PDF (32/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Table 5.9. I²C Timing Specifications (SCL, SDA)
Parameter
Symbol
Test Condition
SCL Clock Frequency
f_SCL
SMBus Timeout
—
Hold Time (Repeated)
START Condition
Low Period of the SCL Clock
HIGH Period of the SCL
Clock
Set-up Time for a Repeated
START Condition
Data Hold Time
Data Set-up Time
Rise Time of Both SDA and
SCL Signals
Fall Time of Both SDA and
SCL Signals
Set-up Time for STOP Con-
dition
Bus Free Time between a
STOP and START Condition
Data Valid Time
Data Valid Acknowledge
Time
t_HD:STA
t_LOW
t_HIGH
t_SU:STA
t_HD:DAT
t_SU:DAT
t_r
t_f
t_SU:STO
t_BUF
t_VD:DAT
t_VD:ACK
When Timeout is Ena-
bled
Standard Mode
100 kbps
Min
Max
—
100
25
35
4.0
—
4.7
—
4.0
—
4.7
—
100
—
250
—
—
1000
—
300
4.0
—
4.7
—
—
3.45
—
3.45
Si5380 Rev D Data Sheet
Electrical Specifications
Fast Mode
Unit
400 kbps
Min
Max
—
400
kHz
25
35
ms
0.6
—
µs
1.3
—
µs
0.6
—
µs
0.6
—
µs
100
—
ns
100
—
ns
20
300
ns
—
300
ns
0.6
—
µs
1.3
—
µs
—
0.9
µs
—
0.9
µs
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