SI5380_16 Datasheet, PDF (29/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Rev D Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
V_DDO = 3.3 V
OUTx_CMOS_DRV=1 I_{OL =} 10 mA
—
—
V_DDO x 0.15
V
OUTx_CMOS_DRV=2 I_{OL =} 12 mA
—
—
OUTx_CMOS_DRV=3 I_{OL =} 17 mA
—
—
V_DDO = 2.5 V
Output Voltage Low ^{1, 2, 3}
V_OL OUTx_CMOS_DRV=1 I_{OL =} 6 mA
—
—
V_DDO x 0.15
V
OUTx_CMOS_DRV=2 I_{OL =} 8 mA
—
—
OUTx_CMOS_DRV=3 I_{OL =} 11 mA
—
—
V_DDO = 1.8 V
OUTx_CMOS_DRV=2 I_{OL =} 4 mA
—
—
V_DDO x 0.15
V
OUTx_CMOS_DRV=3 I_{OL =} 5 mA
—
—
LVCMOS Rise and Fall
tr/tf
Times ³
(20% to 80%)
V_DDO = 3.3 V
V_DDO = 2.5 V
V_DDO = 1.8 V
—
400
600
ps
—
450
600
ps
—
550
750
ps
Notes:
1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the
Si5380 Reference Manual for recommended output register settings.
2. I_OL/I_OH is measured at V_OL/V_OH as shown in the DC test configuration
3. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.
DC Test Configuration
AC Output Test Configuration
IOL/IOH
IDDO
Zs
OUT
OUTb
VOL/VOH
Trace length 5 inches
50
50
499 Ω
4.7 pF
499 Ω
4.7 pF
0.1 uF
56 Ω
50 Ω Scope Input
0.1 uF
56 Ω
50 Ω Scope Input
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