SI5380_16 Datasheet, PDF (12/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Rev D Data Sheet
Functional Description
3.3.7 Zero Delay Mode
A zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs.
The zero delay mode is configured by opening the internal feedback loop through software configuration and closing the loop externally
as shown in the figure below. This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the
output drivers. Any one of the outputs can be fed back to the IN3/FB_IN pins, although using the output driver that achieves the short-
est trace length will help to minimize the input-to-output delay. The OUT9A and IN3/FB_IN pins are recommended for the external feed-
back connection. The FB_IN input pins must be terminated and ac-coupled when zero delay mode is used. A differential external feed-
back path connection is necessary for best performance. The order of the OUT9A and FB_IN polarities is such that they may be routed
on the device side of the PCB without requiring vias or needing to cross each other.
IN0
IN0b
÷P0
IN1
IN1b
÷P1
IN2
÷P2
IN2b
IN3/FB_IN
÷P3
IN3b/FB_INb
Si5380
DSPLL
PD LPF
÷M ÷5
÷N0 t0
÷N1 t1
÷N2 t2
÷N3 t3
÷N4 t4
÷R0A
÷R0
÷R2
÷R8
÷R9
÷R9A
VDDO0
OUT0A
OUT0Ab
OUT0
OUT0b
VDDO2
OUT2
OUT2b
VDDO8
OUT8
OUT8b
OUT9
OUT9b
OUT9A
OUT9Ab
VDDO9
External Feedback Path
Figure 3.6. Si5380 Zero Delay Mode Set-up
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