SI5380_16 Datasheet, PDF (4/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Rev D Data Sheet
Functional Description
3. Functional Description
The Si5380 is a high performance clock generator that is capable of synthesizing up to 10 unique integer related frequencies at any of
the device’s 12 outputs. The output clocks can be generated in free-run mode or synchronized to any one of the four external inputs.
Clock generation is provided by Silicon Laboratories’ 4th generation DSPLL technology which combines frequency synthesis and jitter
attenuation in a highly integrated digital solution that eliminates the need for external VCXO and loop filter components. The Si5380
device is fully configurable using the I2C or SPI serial interface and has in-circuit programmable non-volatile memory.
3.1 Frequency Configuration
The DSPLL provides the synthesis for generating the output clock frequencies which are synchronous to the selected input clock fre-
quency or free-running XTAL. It consists of a phase detector, a programmable digital loop filter, a high-performance ultra-low phase
noise analog 15 GHz VCO, and a user configurable feedback divider. An internal oscillator (OSC) provides the DSPLL with a stable
low-noise clock source for frequency synthesis and for maintaining frequency accuracy in the free-run or holdover modes. The oscillator
simply requires an external, low cost 54 MHz fundamental mode crystal to operate. No other external components are required for fre-
quency generation. A key feature of this DSPLL is that it provides immunity to external noise coupling from power supplies and other
uncontrolled noise sources that normally exist on printed circuit boards.
3.1.1 Si5380 LTE Frequency Configuration
The device’s frequency configuration is fully programmable through the serial interface and can also be stored in non-volatile memory.
The combination of flexible integer dividers and a high frequency VCO allows the device to generate multiple output clock frequencies
for applications that require ultra-low phase noise and spurious performance. At the core of the device are the N dividers which deter-
mine the number of unique frequencies that can be generated from the device. The table below shows a list of some possible output
frequencies for LTE applications. The Si5380’s DSPLL core can generate up to five unique top frequencies. These frequencies are dis-
tributed to the output dividers using a configurable crosspoint mux. The R dividers allow further division for up to 10 unique integer-ratio
related frequencies on the Si5380. The ClockBuilder Pro software utility provides a simple means of automatically calculating the opti-
mum divider values (P, M, N and R) for the frequencies listed in the table below.
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