SI5380_16 Datasheet, PDF (16/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Rev D Data Sheet
Functional Description
3.4.7 Interrupt Pin INTRb
An interrupt pin INTRb indicates a change in state of the status indicators shown in the figure below. All of the status indicators are
maskable to prevent assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the status register that caused the
interrupt. The sticky version of the fault monitors is used for this function to ensure that the fault condition is still available when re-
sponding to the interrupt.
LOS_FLG 0x0012[0]
IN0
OOF_FLG 0x0012[4]
LOS_FLG 0x0012[1]
IN1
OOF_FLG 0x0012[5]
LOS_FLG 0x0012[2]
IN2
OOF_FLG 0x0012[6]
LOS_FLG 0x0012[3]
OOF_FLG 0x0012[7]
LOL_FLG 0x0013[1]
HOLD_FLG 0x0013[5]
CAL_FLG 0x0014[5]
SYSINCAL_FLG 0x0011[0]
LOSXAXB_FLG 0x0011[1]
LOSREF_FLG 0x0011[2]
XAXB_ERR_FLG 0x0011[3]
SMBUS_TIMEOUT_FLG 0x0011[5]
IN3
PLL
Device
Figure 3.13. Interrupt Triggers and Masks
Si5380
INTRb
3.5 Outputs
The Si5380 supports 12 differential output drivers which can be independently configured as differential or LVCMOS.
3.5.1 Output Crosspoint
The output crosspoint allows any of the N dividers to connect to any of the clock outputs.
3.5.2 Output Signal Format
The differential output amplitude and common mode voltage are both fully programmable covering a wide variety of signal formats in-
cluding LVPECL, LVDS, HCSL, and CML. In addition to supporting differential signals, any of the outputs can be configured as
LVCMOS (3.3 V, 2.5 V, or 1.8 V) drivers providing up to 24 single-ended outputs, or any combination of differential and single-ended
outputs.
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