SI5380_16 Datasheet, PDF (30/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Rev D Data Sheet
Electrical Specifications
Table 5.7. Output Serial and Status Pin Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si5380 Output Serial and Status Pins (LOLb, INTRb, SDA/SDIO², A1/SDO)
Output Voltage ^{1, 2}
V_OH
I_OH = –2 mA
V_DDIO x
—
—
V
0.85
V_OL
I_OL = 2 mA
—
—
V_DDIO x
V
0.15
Notes:
1. V_DDIO is determined by the IO_VDD_SEL bit. It is selectable as V_DDA or V_DD. See the Si5380 Reference Manual for more details
on the register settings.
2. The V_OH specification does not apply to the open-drain SDA/SDIO output when the serial interface is in I2C mode or is unused,
with I2C_SEL pulled high internally. V_OL remains valid in all cases.
Table 5.8. Performance Characteristics
Parameter
Symbol
Test Condition
Min
PLL Bandwidth Programming
f_BW
Bandwidth is register
0.1
Range ¹
programmable
Initial Start-Up Time
t_START
Time from power-up to
—
when the device gener-
ates free-running clocks
PLL Lock Time²
t_ACQ
Fastlock enabled
—
F_IN = 19.2 MHz
POR to Serial Interface Ready ³
t_RDY
—
Output Delay Adjustment
t_{DELAY_int}
f_VCO = 14.7456 GHz
—
t_RANGE
±128 / f_VCO
—
Jitter Peaking
J_PK
Measured with a frequen-
—
cy plan running a 24.576
MHz input, 24.576 MHz
output, and a Loop Band-
width of 4 Hz
Jitter Tolerance
J_TOL
Compliant with G.8262
—
Options 1 and 2 Carrier
Frequency = 2.103125
GHz; Jitter Modulation
Frequency = 10 Hz
Maximum Phase Transient Dur-
t_SWITCH
Only valid for a single au-
—
ing a Hitless Switch
tomatic switch between
two input clocks at same
frequency
Only valid for a single
—
manual switch between
two input clocks at same
frequency
Pull-in Range
ω_P
–20
Typ
—
370
280
—
68
8.6
—
3180
—
—
—
Max
Unit
4000
Hz
450
ms
300
ms
15
ms
—
ps
—
ns
0.1
dB
—
UI pk-pk
2.0
ns
1.3
ns
20
ppm
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