SI5380_16 Datasheet, PDF (18/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Rev D Data Sheet
Functional Description
3.5.6 LVCMOS Output Impedance and Drive Strength Selection
Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A source
termination resistor is recommended to help match the selected output impedance to the trace impedance. There are three programma-
ble output impedance selections for each VDDO options as shown in the table below.
Table 3.3. Typical Output Impedance (Z_S)
VDDO
3.3 V
2.5 V
1.8 V
OUTx_CMOS_DRV = 1
38 Ω
43 Ω
—
CMOS_DRIVE_Selection
OUTx_CMOS_DRV = 2
30 Ω
35 Ω
46 Ω
OUTx_CMOS_DRV = 3
22 Ω
24 Ω
31 Ω
3.5.7 LVCMOS Output Signal Swing
The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own
VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers. OUT0 and OUT0A share the same VDDO pin.
OUT9 and OUT9A also share the VDDO pin. All other outputs have their own individual VDDO pins.
3.5.8 LVCMOS Output Polarity
When a driver is configured as an LVCMOS output it generates a clock signal on both pins (OUTx and OUTxb). By default the clock on
the OUTxb pin is generated with the same polarity (in phase) with the clock on the OUTx pin. The polarity of these clocks is configura-
ble enabling complimentary clock generation and/or inverted polarity with respect to other output drivers.
3.5.9 Output Enable/Disable
The OEb pin provides a convenient method of disabling or enabling all of the output drivers at the same time. When the OEb pin is held
high all outputs will be disabled. When held low, the outputs will all be enabled. Outputs in the enabled state can still be individually
disabled through register control.
3.5.10 Output Disable During LOL
By default, a DSPLL that is out of lock will generate either free-running clocks or generate clocks in holdover mode. There is an option
to disable the outputs when a DSPLL is LOL. This option can be useful to force a downstream PLL into holdover.
3.5.11 Output Disable During XAXB_LOS
The internal oscillator circuit (OSC) in combination with the external crystal (XTAL) provides a critical function for the operation of the
DSPLLs. In the event of a crystal failure, the device will assert an XAXB_LOS alarm. By default, all outputs will be disabled during
assertion of the XAXB_LOS alarm. There is an option to leave the outputs enabled during an XAXB_LOS alarm, but the frequency
accuracy and stability will be indeterminate during this fault condition.The internal oscillator circuit (OSC) in combination with the exter-
nal crystal (XTAL) provides a critical function for the operation of the DSPLLs. In the event of a crystal failure, the device will assert an
XAXB_LOS alarm. By default, all outputs will be disabled during assertion of the XAXB_LOS alarm. There is an option to leave the
outputs enabled during an XAXB_LOS alarm, but the frequency accuracy and stability will be indeterminate during this fault condition.
3.5.12 Output Driver State When Disabled
The disabled state of an output driver is configurable as either disable low or disable high.
3.5.13 Synchronous Enable/Disable Feature
The output drivers provide a selectable synchronous enable/disable feature. Output drivers with synchronous disable active will wait
until a clock period has completed before the driver is disabled or enabled. This prevents unwanted shortened pulses from occurring
when enabling or disabling an output. When this feature is turned off, the output clock will disable immediately without waiting for the
clock period to complete.
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