SI5380_16 Datasheet, PDF (17/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

3.5.3 Output Terminations
The output drivers support both ac-coupled and dc-coupled terminations as shown in the following figure.
Si5380 Rev D Data Sheet
Functional Description
DC-coupled LVDS
VDDO = 3.3 V, 2.5 V
OUTx
50
OUTxb
100
50
Si5380
AC-coupled LVDS/LVPECL
VDDO = 3.3 V, 2.5 V, 1.8 V
OUTx
50
OUTxb
100
50
Si5380
Internally
self-biased
VDDO = 3.3 V, 2.5 V, 1.8 V
Si5380
OUTx
OUTxb
AC-coupled HCSL
R1
R1
50
50
R2
R2
VDDRX
Standard
HCSL
Receiver
AC-coupled LVPECL / CML
VDDO = 3.3 V, 2.5 V
Si5380
OUTx
OUTxb
VDD – 1.3 V
50
50
50
50
For VCM = 0.35 V
VDDRX
3.3 V
2.5 V
1.8 V
R1
442 Ω
332 Ω
243 Ω
R2
56.2 Ω
59 Ω
63.4 Ω
Figure 3.14. Supported Output Terminations
3.5.4 Programmable Common Mode Voltage For Differential Outputs
The common mode voltage (V_CM) for the differential modes is programmable in 100 mV increments from 0.7 V to 2.3 V depending on
the voltage available at the output’s VDDO pin. Setting the common mode voltage is useful when dc-coupling the output drivers.
3.5.5 LVCMOS Output Terminations
LVCMOS outputs are dc-coupled with source-side series termination as shown in the figure below.
DC-coupled LVCMOS
VDDO = 3.3V, 2.5V, 1.8V
OUTx
Rs
OUTxb
3.3 V, 2.5 V, 1.8 V
LVCMOS
50
50
Rs
Figure 3.15. LVCMOS Output Terminations
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