SI5380_16 Datasheet, PDF (11/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Rev D Data Sheet
Functional Description
Table 3.2. Manual Input Selection Using IN_SEL[1:0] Pins
IN_SEL[1:0]
0
0
0
1
1
0
1
1
Selected Input
IN0
IN1
IN2
IN3^*
3.3.3 Automatic Input Switching (IN0, IN1, IN2, IN3/FB_IN)
An automatic input selection state machine is available in addition to the manual switching option. In automatic mode, the selection
criteria is based on reference qualification, input priority, and the revertive option. Only references which are valid can be selected by
the automatic state machine. If there are no valid references available, the DSPLL will enter the holdover mode. With revertive switch-
ing enabled, the highest priority input with a valid reference is always selected. If an input with a higher priority becomes valid, then an
automatic switchover to that input will be initiated. With non-revertive switching, the active input will always remain selected while it is
valid. If it becomes invalid, an automatic switchover to a valid input with the highest priority will be initiated.
3.3.4 Hitless Input Switching
Hitless switching is a feature that prevents a phase transient from propagating to the output when switching between two frequency
locked clock inputs that have a fixed phase difference between them. A hitless switch can only occur when the two input frequencies
are frequency locked meaning that they have to be exactly at the same frequency, or have an integer frequency relationship to each
other. When this feature is enabled, the DSPLL simply absorbs the phase difference between the two input clocks during an input
switch. When disabled (normal switching), the phase difference between the two inputs is propagated to the output at a rate determined
by the DSPLL loop bandwidth.
3.3.5 Ramped Input Switching
When switching between two plesiochronous input clocks (i.e., the frequencies are "almost the same" but not quite), ramped input
switching should be enabled to ensure a smooth transition between the two inputs. Ramped input switching avoids frequency transients
and overshoot when switching between frequencies and so is the default switching mode in CBPro. The feature should be turned off
when switching between input clocks that are always frequency locked (i.e., are always the same exact frequency). The same ramp
rate settings are used for both holdover exit and clock switching. For more information on ramped exit from holdover, see 3.1.10 Hold-
over Mode.
3.3.6 Glitchless Input Switching
The DSPLL has the ability of switching between two input clocks that are up to 40 ppm apart in frequency. The DSPLL will pull-in to the
new frequency using the DSPLL loop bandwidth or using the Fastlock loop bandwidth if it is enabled. The loss of lock (LOL) indicator
will be asserted while the DSPLL is pulling-in to the new clock frequency. There will be no output runt pulses generated at the output.
Glitchless input switching is available regardless of whether the hitless switching feature is enabled or disabled.
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