SI5380_16 Datasheet, PDF (26/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Rev D Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. Voltage swing is specified as single-ended mVpp.
OUTx
Vcm
OUTxb
Vcm
Vpp_se
Vpp_se
Vpp_diff = 2*Vpp_se
2. Imposed for phase noise performance.
3. Rise and fall times can be estimated using the following simplified equation: tr/tf_80-20 = ((0.8 – 0.2) * V_{IN_Vpp_se}) / SR.
4. Pulsed CMOS mode is intended primarily for single-end LVCMOS input clocks < 1 MHz, which must be dc-coupled, having a duty
cycle significantly less than 50%. A common application example is a low frequency video frame sync pulse. Since the input
thresholds (VIL, VIH) of the input buffer are non-standard (0.40 and 0.80 V, respectively), refer to the input attenuator circuit for
dc-coupled Pulsed LVCMOS in the in the Si5380 Reference Manual . Otherwise, for standard LVCMOS input clocks, use the
"AC-coupled Single-Ended" mode as shown in Figure 3.14 Supported Output Terminations on page 16.
5. The REFCLK frequency for the Si5380 is fixed at 54 MHz. Contact Silicon Labs technical support for more information.
6. Includes initial tolerance, drift after reflow, change over temperature (–40 °C to +85 °C), V_DD variation, load pulling, and aging.
Table 5.4. Serial and Control Input Pin Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si5380 Serial and Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, SYNCb, PDNb, A1/SDO, SDA/SDIO, SCLK, A0/CSb)
Input Voltage Thresholds
V_IL
—
—
0.3xV_DDIO1
V
V_IH
0.7 x
—
—
V
V_DDIO1
Input Capacitance
C_IN
—
2
—
pF
Input Resistance
I_L
—
20
—
kΩ
Minimum Pulse Width
PW
RSTb, SYNCb, PDNb
100
—
—
ns
Note:
1. V_DDIO is determined by the IO_VDD_SEL bit. It is selectable as V_DDA or V_DD. See the Si5380 Reference Manual for more details
on the register settings.
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