SI5380_16 Datasheet, PDF (38/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

7. Detailed Block Diagram
54MHz
XTAL
IN_SEL
IN0
IN1
IN2
IN3/
FB_IN
XA
XB
OSC
÷P0
÷P1
DSPLL
÷P2
÷P3
I2C_SEL
SDA/SDI
A1/SDO
SCLK
A0/CSb
I²C/
SPI
NVM
÷N0
t0
÷N1
t1
÷N2
t2
÷N3
t3
÷N4
t4
INTRb
LOLb
Status Monitor
Si5380 Rev D Data Sheet
Detailed Block Diagram
Si5380
÷R0A
÷R0
÷R1
÷R2
÷R3
÷R4
÷R5
÷R6
÷R7
÷R8
÷R9
÷R9A
OUT0A
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT9A
PDNb
RSTb
SYNCb OEb
Figure 7.1. Si5380 Block Diagram
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