SI5380_16 Datasheet, PDF (34/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

SCLK
CSb
SDI
SDO
TSU1
TD1
TSU2
TH2
TD2
Si5380 Rev D Data Sheet
Electrical Specifications
TC
TH1
TCS
TD3
Figure 5.2. 4-Wire SPI Serial Interface Timing
Table 5.11. SPI Timing Specifications (3-Wire)
Parameter
SCLK Frequency
SCLK Duty Cycle
SCLK Period
Delay Time, SCLK Fall to SDIO Turn-on
Delay Time, SCLK Fall to SDIO Next-bit
Delay Time, CSb Rise to SDIO Tri-State
Setup Time, CSb to SCLK
Hold Time, SCLK Fall to CSb
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time Between Chip Selects (CSb)
Symbol
f_SPI
T_DC
T_C
T_D1
T_D2
T_D3
T_SU1
T_H1
T_SU2
T_H2
T_CS
Min
Typ
—
—
40
—
50
—
—
—
—
—
—
—
5
—
5
—
5
—
5
—
2
—
TSU1
SCLK
CSb
SDIO
TSU2
TH2
TC
TD1
TD2
Figure 5.3. 3-Wire SPI Serial Interface Timing
Max
Unit
20
MHz
60
%
—
ns
20
ns
15
ns
15
ns
—
ns
—
ns
—
ns
—
ns
—
T_c
TH1
TCS
TD3
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