SI5380_16 Datasheet, PDF (25/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Rev D Data Sheet
Electrical Specifications
Table 5.3. Input Clock Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Standard Input Buffer with Differential or Single-Ended/LVCMOS—AC-coupled (IN0, IN1, IN2, IN3/FB_IN)
Input Frequency Range
f_{IN_DIFF}
Differential
11.52
—
737.28
f_{IN_SE}
All Single-ended Signals
(including LVCMOS)
11.52
—
245.76
Voltage Swing¹
V_IN
Differential AC-coupled
100
F_IN < 245.76 MHz
—
1800
Differential AC-coupled
225
—
1800
245.76 MHz < F_IN <
737.28 MHz
Single-Ended AC-coupled
100
—
3600
F_IN < 245.76 MHz
Slew Rate ^{2, 3}
SR
400
—
—
Duty Cycle
DC
40
—
60
Capacitance
C_IN
—
0.3
—
Input Resistance
R_IN
—
16
—
Pulsed CMOS Input Buffer—DC-coupled (IN0, IN1, IN2, IN3/FB_IN) ⁴
Input Frequency
f_{IN_PULSED_CM}
OS
11.52
—
245.76
Input Voltage Thresholds⁴
V_IL
–0.2
—
0.4
V_IH
0.8
—
—
Slew Rate ^{2, 3}
SR
400
—
—
Duty Cycle
DC
Clock Input
40
—
60
Minimum Pulse Width
PW
Pulse Input
1.6
—
—
Input Resistance
R_IN
—
8
—
REFCLK (applied to XA/XB)
REFCLK Frequency ⁵
f_{IN_REF}
Frequency required for op-
—
54
—
timum performance
Total Frequency Tolerance ⁶
f_RANGE
–100
—
+100
Input Voltage Swing
V_{IN_SE}
365
—
2000
V_{IN_DIFF}
365
—
2500
Slew Rate ^{2 , 3}
SR
Imposed for best phase
400
—
—
noise performance
Input Duty Cycle
DC
40
—
60
Unit
MHz
MHz
mVpp_se
mVpp_se
mVpp_se
V/µs
%
pF
kΩ
MHz
V
V
V/µs
%
ns
kΩ
MHz
ppm
mVpp_se
mVpp_diff
V/µs
%
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