SI5380_16 Datasheet, PDF (13/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Rev D Data Sheet
Functional Description
3.4 Fault Monitoring
All four input clocks (IN0, IN1, IN2, IN3/FB_IN) are monitored for loss of signal (LOS) and out-of-frequency (OOF) as shown in the fig-
ure below. The reference at the XA/XB pins is also monitored for LOS since it provides a critical reference clock for the DSPLL. The
DSPLL also has a Loss Of Lock (LOL) indicator, which is asserted when the DSPLL has lost synchronization with the selected input
clock.
Si5380
XA XB
OSC
IN0
IN0b
IN1
IN1b
IN2
IN2b
IN3/FB_IN
IN3b/FB_INb
÷P0
LOS
OOF
Precision
Fast
÷P1
LOS
OOF
Precision
Fast
÷P2
LOS
OOF
Precision
Fast
÷P3
LOS
OOF
Precision
Fast
LOS
XAXB
LOL
DSPLL
PD LPF
Feedback
Clock
÷M ÷5
Figure 3.7. Si5380 Fault Monitors
3.4.1 Input LOS Detection
The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of
the input LOS circuits have their own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal
sensitivity is configurable using the ClockBuilder Pro utility. The LOS status for each of the monitors is accessible by reading a status
register. The live LOS register always displays the current LOS state and a sticky register always stays asserted until cleared. An option
to disable any of the LOS monitors is also available.
Monitor
LOS
en
LOLOSS
Live
Sticky
Figure 3.8. LOS Status Indicators
3.4.2 XA/XB LOS Detection
An LOS monitor is available to ensure that the external crystal or reference clock is valid. By default, the output clocks are disabled
when XAXB LOS is detected. This feature can be disabled such that the device will continue to produce output clocks when XAXB LOS
is detected. See the 3.5.11 Output Disable During XAXB_LOS section for details.
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