SI5380_16 Datasheet, PDF (20/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Rev D Data Sheet
Functional Description
3.6.1 Power Down Pin (PDNb)
A power down pin is provided to force the device in a low power mode. The device’s configuration will be maintained but no output
clocks will be generated. Most of the internal blocks will be shut down but device communication via the serial interface will still be
available. When the PDNb pin is pulled low the outputs will shut down without glitching (the clock’s complete period will be generated
before shutting down). When PDNb is released the device will start generating clocks without glitches. The device will generate free-
running clocks until the DSPLL has acquired lock to the selected input clock source.
3.7 In-Circuit Programming
The Si5380 is fully configurable using the serial interface (I2C or SPI). At power-up, the device downloads its default register values
from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to gen-
erate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power sup-
ply voltages applied to its VDD and VDDA pins. The NVM is writable two times. Once a new configuration has been written to NVM, the
old configuration is no longer accessible. Refer to the Si5380 Reference Manual for a detailed procedure for writing registers to NVM.
3.8 Serial Interface
Configuration and operation of the Si5380 is controlled by reading and writing registers using the I2C or SPI interface. The I2C_SEL pin
selects I2C or SPI operation. The Si5380 supports communication with a 3.3 V or 1.8 V host by setting the IO_VDD_SEL configuration
bit. The SPI mode supports 4-wire or 3-wire by setting the SPI_3WIRE configuration bit. See the Si5380 Reference Manual for details.
3.9 Custom Factory Preprogrammed Devices
For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered
with a specific configuration written into NVM. A factory pre-programmed device will generate clocks at power-up. Custom, factory-pre-
programmed devices are available. Use the ClockBuilder Pro custom part number wizard (www.silabs.com/clockbuilderpro) to quickly
and easily request and generate a custom part number for your configuration.
In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your
design’s configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local
Silicon Labs sales representative. Samples of your pre-programmed device will ship to you typically within two weeks.
3.10 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-programmed Devices
As with essentially all software utilities, ClockBuilder Pro is continuously updated and enhanced. By registering at www.silabs.com and
opting in for updates to software, you will be notified whenever changes are made and what the impact of those changes are. This
update process will ultimately enable ClockBuilder Pro users to access all features and register setting values documented in this data
sheet and the Si5380 Reference Manual .
However, if you must enable or access a feature or register setting value so that the device starts up with this feature or a register
setting, but the feature or register setting is NOT yet available in CBPro, you must contact a Silicon Labs applications engineer for as-
sistance. Examples of this type of feature or custom setting are the customizable output amplitude and common voltages for the clock
outputs. After careful review of your project file and custom requirements, all Silicon Labs applications engineer will email back your
CBPro project file with your specific features and register settings enabled, using what is referred to as the manual "settings override"
feature of CBPro. "Override" settings to match your request(s) will be listed in your design report file. Examples of setting "overrides" in
a CBPro design report are shown below:
Table 3.4. Setting Overrides
Location
0x0535[0]
0128[6:4]
Name
FORCE_HOLD
OUT6_AMPL
Type
No NVM
User
Target
N/A
OPN and EVB
Dec Value
1
5
Hex Value
0x1
0x5
Once you receive the updated design file, simply open it in CBPro. After you create a custom OPN, the device will begin operation after
startup with the values in the NVM file, including the Silicon Labs-supplied override settings.
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