SI5380_16 Datasheet, PDF (28/53 Pages) Silicon Laboratories – Ultra-Low Phase Noise, 12-output JESD204B Clock Generator

Si5380 Rev D Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. Output amplitude and common mode voltage are programmable through register settings and can be stored in NVM. Each output
driver can be programmed independently. The maximum LVDS single-ended amplitude can be up to 110 mV higher than the TIA/
EIA-644 maximum. Refer to the Si5380 Reference Manual for recommended output register settings. Not all combinations of volt-
age amplitude and common mode voltages settings are possible.
2. Measured for 153.6 MHz carrier frequency. 100 mVpp of sinewave noise added to VDDO when programmed at 3.3 V.
3. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25
MHz. These output frequencies are generated using non-production engineering modes only for test. Refer to application note,
"AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems", for guidance on crosstalk opti-
mization. Note that all active outputs must be terminated when measuring crosstalk
Table 5.6. LVCMOS Clock Output Specifications
Parameter
Symbol
Test Condition
Min
Typ
Output Frequency
0.480
—
Duty Cycle
DC
f_OUT < 100 MHz
48
—
100 MHz < f_OUT < 245.76 MHz
45
—
Output-to-Output Skew
T_SK
Outputs at 153.6 MHz
—
30
V_DDO = 3.3 V
OUTx_CMOS_DRV=1 I_{OH =} –10 mA V_DDO x 0.85
—
OUTx_CMOS_DRV=2 I_{OH =} –12 mA
—
OUTx_CMOS_DRV=3 I_{OH =} –17 mA
—
V_DDO = 2.5 V
Output Voltage High ^{1, 2, 3}
V_OH
OUTx_CMOS_DRV=1 I_{OH =} –6 mA V_DDO x 0.85
—
OUTx_CMOS_DRV=2 I_{OH =} –8 mA
—
OUTx_CMOS_DRV=3 I_{OH =} –11 mA
—
V_DDO = 1.8 V
OUTx_CMOS_DRV=2 I_{OH =} –4 mA V_DDO x 0.85
—
OUTx_CMOS_DRV=3 I_{OH =} –5 mA
—
Max
245.76
52
55
140
—
—
—
—
—
—
—
—
Unit
MHz
%
ps
V
V
V
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