C8051F850-B-GM Datasheet, PDF (81/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
14.5. Power Considerations
The ADC has several power-saving features which can help the user optimize power consumption according to the
needs of the application. The most efficient way to use the ADC for slower sample rates is by using burst mode.
Burst mode dynamically controls power to the ADC and (if used) the internal voltage reference. By completely
powering off these circuits when the ADC is not tracking or converting, the average supply current required for
lower sampling rates is reduced significantly.
The ADC also provides low power options that allow reduction in operating current when operating at low SAR
clock frequencies or with longer tracking times. The internal common-mode buffer can be configured for low power
mode by setting the ADLPM bit in ADC0PWR to 1. Two other fields in the ADC0PWR register (ADBIAS and
ADMXLP) may be used together to adjust the power consumed by the ADC and its multiplexer and reference
buffers, respectively. In general, these options are used together, when operating with a SAR conversion clock
frequency of 4 MHz.
Table 14.2. ADC0 Optimal Power Configuration (8 and 10-bit Mode)
Required
Throughput
325-800 ksps
Reference Source Mode Configuration SAR Clock Speed Other Register Field
Settings
Any
Always-On
(ADEN = 1
ADBMEN = 0)
12.25 MHz
(ADSC = 1)
ADC0PWR = 0x40
ADC0TK = N/A
ADRPT = 0
0-325 ksps
External
Burst Mode
(ADEN = 0
ADBMEN = 1)
12.25 MHz
(ADSC = 1)
ADC0PWR = 0x44
ADC0TK = 0x3A
ADRPT = 0
250-325 ksps
Internal
Burst Mode
(ADEN = 0
ADBMEN = 1)
12.25 MHz
(ADSC = 1)
ADC0PWR = 0x44
ADC0TK = 0x3A
ADRPT = 0
200-250 ksps
Internal
Always-On
(ADEN = 1
ADBMEN = 0)
4.08 MHz
(ADSC = 5)
ADC0PWR = 0xF0
ADC0TK = N/A
ADRPT = 0
0-200 ksps
Internal
Burst Mode
(ADEN = 0
ADBMEN = 1)
4.08 MHz
(ADSC = 5)
ADC0PWR = 0xF4
ADC0TK = 0x34
ADRPT = 0
Notes:
1. For always-on configuration, ADSC settings assume SYSCLK is the internal 24.5 MHz high-frequency oscillator.
Adjust ADSC as needed if using a different source for SYSCLK.
2. ADRPT reflects the minimum setting for this bit field. When using the ADC in Burst Mode, up to 64 samples may be
auto-accumulated per conversion start by adjusting ADRPT.
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Preliminary Rev 0.6