C8051F850-B-GM Datasheet, PDF (238/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

24.7. I2C / SMBus Control Registers
C8051F85x/86x
Register 24.1. SMB0CF: SMBus0 Configuration
Bit
7
6
5
4
3
2
1
0
Name ENSMB
INH
BUSY EXTHOLD SMBTOE SMBFTE
SMBCS
Type
RW
RW
R
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
SFR Address: 0xC1
Table 24.7. SMB0CF Register Bit Descriptions
Bit
Name
Function
7
ENSMB SMBus0 Enable.
This bit enables the SMBus0 interface when set to 1. When enabled, the interface con-
stantly monitors the SDA and SCL pins.
6
INH
SMBus0 Slave Inhibit.
When this bit is set to logic 1, the SMBus0 does not generate an interrupt when slave
events occur. This effectively removes the SMBus0 slave from the bus. Master Mode
interrupts are not affected.
5
BUSY SMBus0 Busy Indicator.
This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to logic 0
when a STOP or free-timeout is sensed.
4
EXTHOLD SMBus0 Setup and Hold Time Extension Enable.
This bit controls the SDA setup and hold times.
0: SDA Extended Setup and Hold Times disabled.
1: SDA Extended Setup and Hold Times enabled.
3
SMBTOE SMBus0 SCL Timeout Detection Enable.
This bit enables SCL low timeout detection. If set to logic 1, the SMBus0 forces Timer 3
to reload while SCL is high and allows Timer 3 to count when SCL goes low. If Timer 3 is
configured to Split Mode, only the High Byte of the timer is held in reload while SCL is
high. Timer 3 should be programmed to generate interrupts at 25 ms, and the Timer 3
interrupt service routine should reset SMBus0 communication.
2
SMBFTE SMBus0 Free Timeout Detection Enable.
When this bit is set to logic 1, the bus will be considered free if SCL and SDA remain high
for more than 10 SMBus clock source periods.
1:0
SMBCS SMBus0 Clock Source Selection.
These two bits select the SMBus0 clock source, which is used to generate the SMBus0
bit rate. See the SMBus clock timing section for additional details.
00: Timer 0 Overflow
01: Timer 1 Overflow
10: Timer 2 High Byte Overflow
11: Timer 2 Low Byte Overflow
Preliminary Rev 0.6
245