C8051F850-B-GM Datasheet, PDF (239/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
Register 24.2. SMB0TC: SMBus0 Timing and Pin Control
Bit
7
6
5
4
3
2
1
0
Name SWAP
Reserved
SDD
Type
RW
R
RW
Reset
0
0
0
0
0
0
0
0
SFR Address: 0xAC
Table 24.8. SMB0TC Register Bit Descriptions
Bit
Name
Function
7
SWAP SMBus0 Swap Pins.
This bit swaps the order of the SMBus0 pins on the crossbar.
0: SDA is mapped to the lower-numbered port pin, and SCL is mapped to the higher-
numbered port pin.
1: SCL is mapped to the lower-numbered port pin, and SDA is mapped to the higher-
numbered port pin.
6:2
Reserved Must write reset value.
1:0
SDD SMBus0 Start Detection Window.
These bits increase the hold time requirement between SDA falling and SCL falling for
START detection.
00: No additional hold time window (0-1 SYSCLK).
01: Increase hold time window to 2-3 SYSCLKs.
10: Increase hold time window to 4-5 SYSCLKs.
11: Increase hold time window to 8-9 SYSCLKs.
246
Preliminary Rev 0.6