C8051F850-B-GM Datasheet, PDF (78/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
A. ADC0 Timing for External Trigger Source
CNVSTR
SAR Clocks
ADTM=1
Low Power
or Convert
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Track
Convert
Low Power
Mode
ADTM=0
Track or Convert
Convert
Track
B. ADC0 Timing for Internal Trigger Source
Write '1' to ADBUSY,
Timer Overflow
SAR
Clocks
ADTM=1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Low Power
or Convert
Track
Convert
Low Power Mode
SAR
Clocks
ADTM=0
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Track or
Convert
Convert
Track
Figure 14.2. 10-Bit ADC Track and Conversion Example Timing (ADBMEN = 0)
14.2.3. Burst Mode
Burst Mode is a power saving feature that allows ADC0 to remain in a low power state between conversions. When
Burst Mode is enabled, ADC0 wakes from a low power state, accumulates 1, 4, 8, 16, 32, or 64 samples using the
internal low-power high-frequency oscillator, then re-enters a low power state. Since the Burst Mode clock is
independent of the system clock, ADC0 can perform multiple conversions then enter a low power state within a
single system clock cycle, even if the system clock is slow (e.g. 80 kHz).
Burst Mode is enabled by setting ADBMEN to logic 1. When in Burst Mode, ADEN controls the ADC0 idle power
state (i.e. the state ADC0 enters when not tracking or performing conversions). If ADEN is set to logic 0, ADC0 is
powered down after each burst. If ADEN is set to logic 1, ADC0 remains enabled after each burst. On each convert
start signal, ADC0 is awakened from its Idle Power State. If ADC0 is powered down, it will automatically power up
and wait the programmable Power-Up Time controlled by the ADPWR bits. Otherwise, ADC0 will start tracking and
converting immediately. Figure 14.3 shows an example of Burst Mode Operation with a slow system clock and a
repeat count of 4.
When Burst Mode is enabled, a single convert start will initiate a number of conversions equal to the repeat count.
When Burst Mode is disabled, a convert start is required to initiate each conversion. In both modes, the ADC0 End
of Conversion Interrupt Flag (ADINT) will be set after “repeat count” conversions have been accumulated. Similarly,
the Window Comparator will not compare the result to the greater-than and less-than registers until “repeat count”
conversions have been accumulated.
In Burst Mode, tracking is determined by the settings in ADPWR and ADTK. Settling time requirements may need
adjustment in some applications. Refer to “14.2.4. Settling Time Requirements” on page 82 for more details.
Preliminary Rev 0.6
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