C8051F850-B-GM Datasheet, PDF (10/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
Table 1.3. Reset and Supply Monitor
Parameter
V_DD Supply Monitor Threshold
Power-On Reset (POR) Threshold
V_DD Ramp Time
Reset Delay from POR
Reset Delay from non-POR source
RST Low Time to Generate Reset
Missing Clock Detector Response
Time (final rising edge to reset)
Missing Clock Detector Trigger 
Frequency
V_DD Supply Monitor Turn-On Time
Symbol
Test Condition
V_VDDM
V_POR
t_RMP
t_POR
t_RST
Rising Voltage on V_DD
Falling Voltage on V_DD
Time to V_DD > 2.2 V
Relative to V_DD >
V_POR
Time between release
of reset source and
code execution
t_RSTL
t_MCD
F_SYSCLK > 1 MHz
F_MCD
t_MON
Min
1.85
—
0.8
10
3
—
15
—
—
—
Typ
1.95
1.4
—
—
—
30
—
0.625
7.5
2
Max
2.1
—
1.3
3000
TBD
—
—
1.2
13
—
Unit
V
V
V
µs
ms
µs
µs
ms
kHz
µs
Table 1.4. Flash Memory
Parameter
Symbol
Test Condition
Min
Typ
Max Units
Write Time¹
Erase Time¹
V_DD Voltage During Programming²
t_WRITE
t_ERASE
V_PROG
One Byte
One Page
TBD
20
TBD
µs
TBD
5
TBD
ms
2.2
—
3.6
V
Endurance (Write/Erase Cycles)
N_WE
20k 100k
— Cycles
Notes:
1. Does not include sequencing time before and after the write/erase operation, which may be multiple SYSCLK cycles.
2. Flash can be safely programmed at any voltage above the supply monitor threshold (V_VDDM).
3. Data Retention Information is published in the Quarterly Quality and Reliability Report.
10
Preliminary Rev 0.6