C8051F850-B-GM Datasheet, PDF (172/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
21. Port I/O (Port 0, Port 1, Port 2, Crossbar, and Port Match)
Digital and analog resources on the C8051F85x/86x family are externally available on the device’s multi-purpose I/
O pins. Port pins P0.0-P1.7 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital
resources through the crossbar, or assigned to an analog function. Port pins P2.0 and P2.1 can be used as GPIO.
Port pin P2.0 is shared with the C2 Interface Data signal (C2D). The designer has complete control over which
functions are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is
achieved through the use of a priority crossbar decoder. Note that the state of a port I/O pin can always be read in
the corresponding port latch, regardless of the crossbar settings.
The crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 21.2 and Figure 21.3). The registers XBR0, XBR1 and XBR2 are used to select internal digital functions.
The port I/O cells are configured as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT,
where n = 0,1). Additionally, each bank of port pins (P0, P1, and P2) have two selectable drive strength settings.
2
UART0
4
SPI0
2
SMBus0
2
CMP0 Out
2
CMP1 Out
1
SYSCLK
3
PCA (CEXn)
1
PCA (ECI)
1
Timer 0
1
Timer 1
1
Timer 2
Priority Crossbar
Decoder
ADC0 In
CMP0/1 In
Port Match
INT0 / INT1
Port 0
Control
&
Config
Port 1
Control
&
Config
Port 2
Control
&
Config
Figure 21.1. Port I/O Functional Block Diagram
P0.0 / VREF
P0.1 / AGND
P0.2
P0.3 / EXTCLK
P0.4
P0.5
P0.6 / CNVSTR
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0 / C2D
P2.1
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Preliminary Rev 0.6