C8051F850-B-GM Datasheet, PDF (27/290 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

C8051F85x/86x
2.7. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset
state, the following occur:
The core halts program execution.
Module registers are initialized to their defined reset values unless the bits reset only with a power-on
reset.
External port pins are forced to a known state.
Interrupts and timers are disabled.
All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a
power-on reset. The contents of RAM are unaffected during a reset; any previously stored data is preserved as
long as power is not lost.
The Port I/O latches are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For
VDD Supply Monitor and power-on resets, the RST pin is driven low until the device exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the internal low-
power oscillator. The Watchdog Timer is enabled with the Low Frequency Oscillator (LFO0) as its clock source.
Program execution begins at location 0x0000.
2.8. On-Chip Debugging
The C8051F85x/86x devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow flash program-
ming and in-system debugging with the production part installed in the end application. The C2 interface uses a
clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information between the device and a
host system. See the C2 Interface Specification for details on the C2 protocol.
Preliminary Rev 0.6
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